[ DevCourseWeb.com ] Udemy - Building Custom AXI Interface Peripherals for ZYNQ Devices

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[ DevCourseWeb.com ] Udemy - Building Custom AXI Interface Peripherals for ZYNQ Devices

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文件大小： 2.96G
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收录时间：2023-12-28
最近下载：2025-07-23

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文件列表

  • ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/37 - Using Vivado Interrupt Template Code P2.mp4 224.0 MB
  • ~Get Your Files Here !/8 - Adding Master Interface/45 - Creating Master Interface with Vivado Template P1.mp4 170.4 MB
  • ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/42 - Blinking Effect with Interrupt.mp4 158.1 MB
  • ~Get Your Files Here !/6 - Adding Interrupts to Slave Lite Interfaces/33 - Adding Interrupt with RTL P2.mp4 156.5 MB
  • ~Get Your Files Here !/10 - AXI Stream Master Interface with Vivado Template/55 - Creating AXIS Master Interface P1.mp4 152.3 MB
  • ~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/49 - Building AXIS Slave Interface P1.mp4 145.6 MB
  • ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/36 - Using Vivado Interrupt Template Code P1.mp4 104.9 MB
  • ~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/23 - Analyzing Signals on ILA Probe.mp4 102.9 MB
  • ~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/25 - Add Existing RTL Delay Generator P1.mp4 98.3 MB
  • ~Get Your Files Here !/6 - Adding Interrupts to Slave Lite Interfaces/32 - Adding Interrupt with RTL P1.mp4 94.8 MB
  • ~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/21 - Other Signals in Slave Lite Interface.mp4 93.9 MB
  • ~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/27 - Adding Existing RTL Multiplier P1.mp4 87.1 MB
  • ~Get Your Files Here !/6 - Adding Interrupts to Slave Lite Interfaces/31 - Fundamentals of Interrupt C Application.mp4 84.5 MB
  • ~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/7 - Slave Lite Interface without I O Ports P4 Creating C Application.mp4 80.0 MB
  • ~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/50 - Building AXIS Slave Interface P2.mp4 68.7 MB
  • ~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/52 - Building Complex FSM with existing FSM for AXIS.mp4 67.1 MB
  • ~Get Your Files Here !/8 - Adding Master Interface/46 - Creating Master Interface with Vivado Template P2.mp4 65.7 MB
  • ~Get Your Files Here !/11 - AXIS Slave Interface with Verilog/60 - Building AXIS Slave Interface with Verilog P2.mp4 64.6 MB
  • ~Get Your Files Here !/12 - AXIS Master Slave Interface with Verilog/64 - Building AXIS Master Slave Interface with Verilog P1.mp4 60.3 MB
  • ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/39 - Modifying Delay of the Vivado Interrupt Template.mp4 58.0 MB
  • ~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/4 - Slave Lite Interface without I O Ports P1 Creating IP.mp4 58.0 MB
  • ~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/29 - Adding Exisitng RTL COMPLEX FSM P1.mp4 57.4 MB
  • ~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/11 - Adding Output port to Slave Lite Interface P1.mp4 52.8 MB
  • ~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/15 - Adding Input and Output ports to Slave Lite Interface P2.mp4 51.7 MB
  • ~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/5 - Slave Lite Interface without I O Ports P2 Creating IP.mp4 51.7 MB
  • ~Get Your Files Here !/1 - Section 0 Course Framework/2 - Course Framework.mp4 50.0 MB
  • ~Get Your Files Here !/12 - AXIS Master Slave Interface with Verilog/65 - Building AXIS Master Slave Interface with Verilog P2.mp4 47.3 MB
  • ~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/14 - Adding Input and Output ports to Slave Lite Interface P1.mp4 47.0 MB
  • ~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/26 - Add Existing RTL Delay Generator P2.mp4 45.9 MB
  • ~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/28 - Adding Existing RTL Multiplier P2.mp4 45.4 MB
  • ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/40 - Generating Continuous Interrupt P1.mp4 43.5 MB
  • ~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/6 - Slave Lite Interface without I O Ports P3 Creating IP.mp4 41.1 MB
  • ~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/8 - Slave Lite Interface without I O Ports P5 Creating C Application.mp4 40.2 MB
  • ~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/22 - Block Design used in Demonstration.mp4 39.8 MB
  • ~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/12 - Adding Output port to Slave Lite Interface P2.mp4 38.9 MB
  • ~Get Your Files Here !/11 - AXIS Slave Interface with Verilog/59 - Building AXIS Slave Interface with Verilog P1.mp4 38.9 MB
  • ~Get Your Files Here !/10 - AXI Stream Master Interface with Vivado Template/56 - Creating AXIS Master Interface P2.mp4 37.0 MB
  • ~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/13 - Adding Output port to Slave Lite Interface P3.mp4 35.2 MB
  • ~Get Your Files Here !/13 - Understanding Common Errors/69 - Common Error 2.mp4 26.0 MB
  • ~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/18 - Understanding Mandatory Signal Master Write to Slave (Writing Ops) P1.mp4 25.7 MB
  • ~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/19 - Understanding Mandatory Signal Master Write to Slave (Writing Ops) P2.mp4 25.1 MB
  • ~Get Your Files Here !/11 - AXIS Slave Interface with Verilog/61 - Building AXIS Slave Interface with Verilog P3.mp4 24.5 MB
  • ~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/16 - Adding Input and Output ports to Slave Lite Interface P3.mp4 24.1 MB
  • ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/41 - Generating Continuous Interrupt P2.mp4 22.9 MB
  • ~Get Your Files Here !/13 - Understanding Common Errors/68 - Common Error 1.mp4 20.0 MB
  • ~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/20 - Understanding Mandatory Signal Master read from Slave (Reading Ops).mp4 12.6 MB
  • ~Get Your Files Here !/1 - Section 0 Course Framework/1 - Interface Type.mp4 11.9 MB
  • ~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/24 - Agenda.mp4 5.2 MB
  • ~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/48 - Agenda.mp4 2.8 MB
  • ~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/10 - Agenda.mp4 2.8 MB
  • ~Get Your Files Here !/12 - AXIS Master Slave Interface with Verilog/63 - Agenda.mp4 2.5 MB
  • ~Get Your Files Here !/10 - AXI Stream Master Interface with Vivado Template/54 - Agenda.mp4 2.4 MB
  • ~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/17 - Agenda.mp4 2.4 MB
  • ~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/3 - Agenda.mp4 2.4 MB
  • ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/35 - Agenda.mp4 2.2 MB
  • ~Get Your Files Here !/8 - Adding Master Interface/44 - Agenda.mp4 2.2 MB
  • ~Get Your Files Here !/11 - AXIS Slave Interface with Verilog/58 - Agenda.mp4 2.1 MB
  • ~Get Your Files Here !/6 - Adding Interrupts to Slave Lite Interfaces/30 - Agenda.mp4 2.0 MB
  • ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/37 - Using Vivado Interrupt Template Code P2 English.vtt 29.8 kB
  • ~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/49 - Building AXIS Slave Interface P1 English.vtt 24.6 kB
  • ~Get Your Files Here !/10 - AXI Stream Master Interface with Vivado Template/55 - Creating AXIS Master Interface P1 English.vtt 22.9 kB
  • ~Get Your Files Here !/8 - Adding Master Interface/45 - Creating Master Interface with Vivado Template P1 English.vtt 21.8 kB
  • ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/42 - Blinking Effect with Interrupt English.vtt 19.2 kB
  • ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/36 - Using Vivado Interrupt Template Code P1 English.vtt 18.3 kB
  • ~Get Your Files Here !/6 - Adding Interrupts to Slave Lite Interfaces/33 - Adding Interrupt with RTL P2 English.vtt 18.0 kB
  • ~Get Your Files Here !/12 - AXIS Master Slave Interface with Verilog/64 - Building AXIS Master Slave Interface with Verilog P1 English.vtt 17.7 kB
  • ~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/25 - Add Existing RTL Delay Generator P1 English.vtt 16.0 kB
  • ~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/23 - Analyzing Signals on ILA Probe English.vtt 15.8 kB
  • ~Get Your Files Here !/6 - Adding Interrupts to Slave Lite Interfaces/31 - Fundamentals of Interrupt C Application English.vtt 14.8 kB
  • ~Get Your Files Here !/6 - Adding Interrupts to Slave Lite Interfaces/32 - Adding Interrupt with RTL P1 English.vtt 14.0 kB
  • ~Get Your Files Here !/11 - AXIS Slave Interface with Verilog/60 - Building AXIS Slave Interface with Verilog P2 English.vtt 13.5 kB
  • ~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/27 - Adding Existing RTL Multiplier P1 English.vtt 12.9 kB
  • ~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/21 - Other Signals in Slave Lite Interface English.vtt 12.3 kB
  • ~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/7 - Slave Lite Interface without I O Ports P4 Creating C Application English.vtt 11.5 kB
  • ~Get Your Files Here !/11 - AXIS Slave Interface with Verilog/59 - Building AXIS Slave Interface with Verilog P1 English.vtt 11.2 kB
  • ~Get Your Files Here !/Building Custom AXI Interface Peripherals for ZYNQ Devices.jpg 11.0 kB
  • ~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/4 - Slave Lite Interface without I O Ports P1 Creating IP English.vtt 10.3 kB
  • ~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/29 - Adding Exisitng RTL COMPLEX FSM P1 English.vtt 10.2 kB
  • ~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/52 - Building Complex FSM with existing FSM for AXIS English.vtt 9.9 kB
  • ~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/18 - Understanding Mandatory Signal Master Write to Slave (Writing Ops) P1 English.vtt 8.7 kB
  • ~Get Your Files Here !/1 - Section 0 Course Framework/2 - Course Framework English.vtt 8.6 kB
  • ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/39 - Modifying Delay of the Vivado Interrupt Template English.vtt 8.5 kB
  • ~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/11 - Adding Output port to Slave Lite Interface P1 English.vtt 8.3 kB
  • ~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/5 - Slave Lite Interface without I O Ports P2 Creating IP English.vtt 8.1 kB
  • ~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/50 - Building AXIS Slave Interface P2 English.vtt 7.8 kB
  • ~Get Your Files Here !/8 - Adding Master Interface/46 - Creating Master Interface with Vivado Template P2 English.vtt 7.7 kB
  • ~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/14 - Adding Input and Output ports to Slave Lite Interface P1 English.vtt 7.7 kB
  • ~Get Your Files Here !/12 - AXIS Master Slave Interface with Verilog/65 - Building AXIS Master Slave Interface with Verilog P2 English.vtt 7.4 kB
  • ~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/19 - Understanding Mandatory Signal Master Write to Slave (Writing Ops) P2 English.vtt 6.8 kB
  • ~Get Your Files Here !/Building Custom AXI Interface Peripherals for ZYNQ Devices.txt 6.6 kB
  • ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/40 - Generating Continuous Interrupt P1 English.vtt 6.2 kB
  • ~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/26 - Add Existing RTL Delay Generator P2 English.vtt 6.1 kB
  • ~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/6 - Slave Lite Interface without I O Ports P3 Creating IP English.vtt 6.0 kB
  • ~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/15 - Adding Input and Output ports to Slave Lite Interface P2 English.vtt 5.7 kB
  • ~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/22 - Block Design used in Demonstration English.vtt 5.2 kB
  • ~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/12 - Adding Output port to Slave Lite Interface P2 English.vtt 5.1 kB
  • ~Get Your Files Here !/10 - AXI Stream Master Interface with Vivado Template/56 - Creating AXIS Master Interface P2 English.vtt 5.1 kB
  • ~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/8 - Slave Lite Interface without I O Ports P5 Creating C Application English.vtt 4.9 kB
  • ~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/28 - Adding Existing RTL Multiplier P2 English.vtt 4.8 kB
  • ~Get Your Files Here !/11 - AXIS Slave Interface with Verilog/61 - Building AXIS Slave Interface with Verilog P3 English.vtt 4.7 kB
  • ~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/13 - Adding Output port to Slave Lite Interface P3 English.vtt 4.3 kB
  • ~Get Your Files Here !/13 - Understanding Common Errors/69 - Common Error 2 English.vtt 4.2 kB
  • ~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/20 - Understanding Mandatory Signal Master read from Slave (Reading Ops) English.vtt 4.0 kB
  • ~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/53 - Code.html 3.4 kB
  • ~Get Your Files Here !/13 - Understanding Common Errors/68 - Common Error 1 English.vtt 2.8 kB
  • ~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/16 - Adding Input and Output ports to Slave Lite Interface P3 English.vtt 2.8 kB
  • ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/41 - Generating Continuous Interrupt P2 English.vtt 2.7 kB
  • ~Get Your Files Here !/12 - AXIS Master Slave Interface with Verilog/67 - Code and BD.html 2.6 kB
  • ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/43 - Code.html 2.4 kB
  • ~Get Your Files Here !/11 - AXIS Slave Interface with Verilog/62 - Code and BD.html 2.2 kB
  • ~Get Your Files Here !/6 - Adding Interrupts to Slave Lite Interfaces/34 - Code.html 2.2 kB
  • ~Get Your Files Here !/12 - AXIS Master Slave Interface with Verilog/66 - Code and BD.html 2.1 kB
  • ~Get Your Files Here !/1 - Section 0 Course Framework/1 - Interface Type English.vtt 2.0 kB
  • ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/38 - Code.html 1.9 kB
  • ~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/24 - Agenda English.vtt 1.5 kB
  • ~Get Your Files Here !/10 - AXI Stream Master Interface with Vivado Template/57 - Code.html 1.3 kB
  • ~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/48 - Agenda English.vtt 974 Bytes
  • ~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/17 - Agenda English.vtt 964 Bytes
  • ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/35 - Agenda English.vtt 945 Bytes
  • ~Get Your Files Here !/12 - AXIS Master Slave Interface with Verilog/63 - Agenda English.vtt 917 Bytes
  • ~Get Your Files Here !/6 - Adding Interrupts to Slave Lite Interfaces/30 - Agenda English.vtt 899 Bytes
  • ~Get Your Files Here !/8 - Adding Master Interface/44 - Agenda English.vtt 792 Bytes
  • ~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/9 - C Code.html 791 Bytes
  • ~Get Your Files Here !/10 - AXI Stream Master Interface with Vivado Template/54 - Agenda English.vtt 775 Bytes
  • ~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/51 - Code.html 775 Bytes
  • ~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/10 - Agenda English.vtt 746 Bytes
  • ~Get Your Files Here !/11 - AXIS Slave Interface with Verilog/58 - Agenda English.vtt 613 Bytes
  • ~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/3 - Agenda English.vtt 583 Bytes
  • ~Get Your Files Here !/8 - Adding Master Interface/47 - Code.html 576 Bytes
  • ~Get Your Files Here !/Bonus Resources.txt 386 Bytes
  • Get Bonus Downloads Here.url 182 Bytes

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